Single cycle processor
Multi-cycle processor
Pipelined processor
| CPI | CT | |
| Single Cycle | 1 | max(inst) |
| Multi-cycle lw (IF, DE, EX, MEM, WB) sw (IF, DE, EX, MEM) beq (IF, DE, EX) r-type (IF, DE, EX, WB) | 3-5 5 4 3 4 | max(stage) |
| Pipelined | 1 | max(stage) |
[Computer Architecture] Processor Design
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Byung Hoon Ahn 